Optimal Temporal Blocking for Stencil Computation
Optimal Temporal Blocking for Stencil Computation
复制标题
模板计算的最佳时间阻塞
DOI：
10.1016/j.procs.2015.05.315
复制
发表时间：
2015
期刊：
影响因子：
--
通讯作者：
J. Makino
中科院分区：
文献类型：
--
作者：
T. Muranushi;J. Makino
时间分块是一类算法，它通过“分块”多个时间步来减少给定模板计算所需的内存带宽（B/Fratio）。在本文中，我们证明了在一定条件下，存在一个较低的限制，减少的B/脂肪的时间阻塞。我们介绍了PiTCH平铺，时间块方法，实现了最优的B/FR比的一个例子。我们估计的性能PiTCH平铺各种模板应用程序在几个现代CPU。我们表明，PiTCH平铺实现1.5<2倍betterB/F减少在三维应用程序中，相比其他时间块计划。我们还表明，PiTCH平铺可以从大多数考虑的模板应用程序中删除带宽瓶颈。
Temporal blocking is a class of algorithms which reduces the required memory bandwidth (B/Fratio) of a given stencil computation, by “blocking” multiple time steps. In this paper, we prove that a lower limit exists for the reduction of theB/Fattainable by temporal blocking, under certain conditions. We introduce the PiTCH tiling, an example of temporal blocking method that achieves the optimalB/Fratio. We estimate the performance of PiTCH tiling for various stencil applications on several modern CPUs. We show that PiTCH tiling achieves 1.5<2 times betterB/Freduction in three-dimensional applications, compared to other temporal blocking schemes. We also show that PiTCH tiling can remove the bandwidth bottleneck from most of the stencil applications considered.