SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading
SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading
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DOI：
10.1145/2000064.2000094
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发表时间：
2011-06
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通讯作者：
Wing-Kei S. Yu;Ruirui C. Huang;Sarah Q. Xu;Sung-En Wang;E. Kan;G. Edward Suh
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文献类型：
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作者：
Wing-Kei S. Yu;Ruirui C. Huang;Sarah Q. Xu;Sung-En Wang;E. Kan;G. Edward Suh
大型寄存器文件在GPU等高度多线程架构中很常见。本文提出了一种将嵌入式DRAM与SRAM单元紧密集成的混合存储器设计，主要应用于减少多线程寄存器文件的面积和功耗。在混合存储器中，每个SRAM单元增加有多个DRAM单元，使得多个位可以存储在每个单元中。由于紧凑的DRAM单元，与具有相同容量的SRAM阵列相比，这种配置导致显著的面积和能量节省。另一方面，混合存储器需要显式数据移动以便访问DRAM上下文。为了最大限度地减少上下文切换的影响，我们引入回写缓冲区，后台上下文切换，上下文感知线程调度，处理器流水线和调度器。GPU基准测试套件的电路和架构模拟显示，与传统SRAM实现相比，寄存器文件面积（38%）和能源（68%）显著节省，性能损失最小（1.4%）。
Large register files are common in highly multi-threaded architectures such as GPUs. This paper presents a hybrid memory design that tightly integrates embedded DRAM into SRAM cells with a main application to reducing area and power consumption of multi-threaded register files. In the hybrid memory, each SRAM cell is augmented with multiple DRAM cells so that multiple bits can be stored in each cell. This configuration results in significant area and energy savings compared to the SRAM array with the same capacity due to compact DRAM cells. On other hand, the hybrid memory requires explicit data movements in order to access DRAM contexts. In order to minimize context switching impact, we introduce write-back buffers, background context switching, and context-aware thread scheduling, to the processor pipeline and the scheduler. Circuit and architecture simulations of GPU benchmarks suites show significant savings in register file area (38%) and energy (68%) over the traditional SRAM implementation, with minimal (1.4%) performance loss.