A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance
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DOI：
10.1109/jssc.2008.917372
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发表时间：
2008-03
影响因子：
5.4
通讯作者：
B. Helal;M. Straayer;Gu-Yeon Wei;M. Perrott
中科院分区：
文献类型：
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作者：
B. Helal;M. Straayer;Gu-Yeon Wei;M. Perrott
本文提出了一种主要是数字乘法延迟锁定环（MDLL）的架构，利用一个新的时间-数字转换器（TDC）和相关的双采样技术，以实现亚皮秒抖动性能。所提出的结构的主要优点是，它提供了一种高度数字化的技术，以减少MDLL输出中的确定性抖动，同时对相关调谐电路中的失配和失调具有低灵敏度。基于门控环形振荡器（GRO）的TDC结构预期也有益于其它PLL/DLL应用，这是由于其加扰和一阶噪声对其相关联的量化噪声进行整形的事实。测量结果的自定义MDLL原型，乘以50 MHz的参考频率为1.6 GHz的928 fs均方根抖动性能。该原型由两个0.13妈妈集成电路，其中有一个合并的有效面积为0.06平方毫米和合并的核心功率为5.1毫瓦，除了一个FPGA板，一个离散的DAC，和一个简单的RC滤波器。
This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 mum integrated circuits, which have a combined active area of 0.06 mm2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.