A design for high-speed low-power CMOS fully parallel content-addressable memory macros
A design for high-speed low-power CMOS fully parallel content-addressable memory macros
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DOI：
10.1109/4.924858
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发表时间：
2001-06
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影响因子：
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通讯作者：
H. Miyatake;Masahiro Tanaka;Yotaro Mori
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文献类型：
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作者：
H. Miyatake;Masahiro Tanaka;Yotaro Mori
描述了一种用于CMOS ASIC应用的高速低功耗全并行内容可寻址存储器（CAM）宏的设计。该设计支持的配置范围从64字的8位到2048字的64位，并实现了约7.5纳秒的搜索访问时间在CAM宏的0.35-/spl亩/米3.3 V标准CMOS ASIC技术。一个新的CAM单元与pMOS匹配线驱动器减少搜索冲击电流和功耗，允许NOR型匹配线结构适合高速搜索操作。它还表明，CAM单元具有其他优点，导致一个简单的高速电流节省架构。匹配线上的小信号由具有高速和低功耗特性以及锁存功能的单端读出放大器检测。相同类型的读出放大器用于快速读取操作，在典型条件下实现5 ns的访问时间。为了在搜索操作中进一步节省电流，基于有效位状态来控制匹配线的预充电。此外，具有优化尺寸和控制的双位开关降低了电流。测试芯片上256/spl次/54配置的CAM宏显示，在典型条件下，搜索访问时间为7.3 ns，功耗性能指标为131 fJ/bit/search。
Described is a design for high-speed low-power-consumption fully parallel content-addressable memory (CAM) macros for CMOS ASIC applications. The design supports configurations ranging from 64 words by 8 bits to 2048 words by 64 bits and achieves around 7.5-ns search access times in CAM macros on a 0.35-/spl mu/m 3.3-V standard CMOS ASIC technology. A new CAM cell with a pMOS match-line driver reduces search rush current and power consumption, allowing a NOR-type match-line structure suitable for high-speed search operations. It is also shown that the CAM cell has other advantages that lead to a simple high-speed current-saving architecture. A small signal on the match line is detected by a single-ended sense amplifier which has both high-speed and low-power characteristics and a latch function. The same type of sense amplifier is used for a fast read operation, realizing 5-ns access time under typical conditions. For further current savings in search operations, the precharging of the match line is controlled based on the valid bit status. Also, a dual bit switch with optimized size and control reduces the current. CAM macros of 256/spl times/54 configuration on test chips showed 7.3-ns search access time with a power-performance metric of 131 fJ/bit/search under typical conditions.