Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration
Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration
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基于流的 FPGA 加速器上模板计算的性能建模，实现高效设计空间探索
DOI：
10.1587/transinf.2014rcp0013
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
K. Oguri
中科院分区：
文献类型：
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作者：
Keisuke Dohi;Koji Okina;Rie Soejima;Yuichiro Shibata;K. Oguri
在本文中，我们讨论了三维模板计算在FPGA加速器上的性能建模和高级合成环境，旨在有效地探索用户空间的设计参数。首先，我们分析了资源利用率和性能之间的关系，并建立了数学模型。然后，为了评估我们提出的模型，我们通过使用MaxCompiler（用于fpga的高级合成工具）和MaxGenFD（用于有限差分方程求解器的MaxCompiler的特定领域框架）实现热传导模拟作为基准应用程序。不同建筑设计参数设置下的实验结果表明，利用该模型可以系统地找到管道结构设计参数的最佳组合。讨论了改变算法精度和使用数据流压缩的影响。
SUMMARY In this paper, we discuss performance modeling of 3-D stencil computing on an FPGA accelerator with a high-level synthesis environment, aiming for e ffi cient exploration of user-space design parameters. First, we analyze resource utilization and performance to formulate these relationships as mathematical models. Then, in order to evaluate our proposed models, we implement heat conduction simulations as a benchmark application, by using MaxCompiler, which is a high-level synthesis tool for FPGAs, and MaxGenFD, which is a domain specific framework of the MaxCompiler for finite-di ff erence equation solvers. The experimental results with various settings of architectural design parameters show the best combination of design parameters for pipeline structure can be systematically found by using our models. The e ff ects of changing arithmetic accuracy and using data stream compression are also discussed.