A simulation of a memory subsystem using a highly energy-efficient but erroneous MRAM
A simulation of a memory subsystem using a highly energy-efficient but erroneous MRAM
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使用高能效但错误的 MRAM 模拟内存子系统
DOI：
10.1109/candarw53999.2021.00027
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
Sato Yukinori
中科院分区：
文献类型：
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作者：
Saito Daiki;Hirofuchi Takahiro;Arai Hiroko;Sato Yukinori
为了降低计算机的主存储器的功耗，使用MRAM（磁阻随机存取存储器）代替DRAM是有吸引力的，因为MRAM不需要周期性刷新能量，同时实现足够小的读/写延迟。在各种类型的MRAM器件中，VC-MRAM（压控MRAM）具有实现大规模节能存储器子系统的巨大潜力。其写入能量比STT-MRAM小2倍数量级。然而，VC-MRAM的问题在于其写入错误率（即，10 - 4与当今的典型技术）比主存储器所要求的可接受的错误率（即，10−9）。在本文中，我们调查是否来自一个错误的内存设备的错误导致的问题，在实际的程序执行中的内存子系统与分层高速缓存存储器。我们开发了一个内存子系统模拟器，模仿的多级缓存和主存储器的结构的基础上的VC-MRAM模型，并观察整个基准程序的执行过程中的主存储器中的单元级操作。从结果中，我们发现位损坏的数量很大程度上取决于该高速缓存的大小和设备的错误模型。这是因为通过该高速缓存可以显著减少存储器访问本身的次数。此外，我们观察到，发生的位损坏超过3位，不能正确处理的汉明ECC码很少发生。这一观察使我们认识到，如果在具有大型高速缓存存储器的CPU上执行，则具有汉明ECC的VC-MRAM可以在某些应用中用作主存。
In order to reduce power consumption of the main memory of computers, the use of MRAM (magnetoresistive random access memory) instead of DRAM is attractive, since MRAM does not require periodic refresh energy while achieving sufficiently small read/write latencies. Among various types of MRAM devices, VC-MRAM (voltage-controlled MRAM) has a great potential to realize massively energy-efficient memory subsystems. Its write energy is 2 times orders of magnitudes smaller than that of STT-MRAM. The problem with VC-MRAM, however, is that its write error rate (i.e., 10−4with today’s typical technologies) is much higher than the acceptable error rate that has been supposed to be required for the main memory (i.e., 10−9). In this paper, we investigate whether such errors derived from an erroneous memory device cause a problem in actual program execution in the memory subsystem with hierarchical cache memory. We develop a memory subsystem simulator that mimics the structure of the multi-level caches and the main memory based on a VC-MRAM model, and observe cell-level operations in the main memory throughout the execution of benchmark programs. From results, we find the number of bit corruptions depends greatly on the cache size and the error model of the device. This is because the number of memory accesses itself can be significantly reduced by passing through the cache. Furthermore, we observe that the occurrences of bit corruptions more than 3 bits that cannot be handled properly by the hamming ECC codes seldom happen. This observation leads us to the insight that VC-MRAM with Hamming ECC can be used as main memory in some applications if these are executed on CPUs with a large cache memory.