Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs
复制标题
DOI：
10.1109/nocs.2010.16
复制
发表时间：
2010-05
期刊：
影响因子：
--
通讯作者：
Hiroki Matsutani;M. Koibuchi;Daisuke Ikebuchi;K. Usami;Hiroshi Nakamura;H. Amano
中科院分区：
文献类型：
--
作者：
Hiroki Matsutani;M. Koibuchi;Daisuke Ikebuchi;K. Usami;Hiroshi Nakamura;H. Amano
本文提出了一种超细粒度的片上路由器运行时功率门控，可以根据应用的工作负载单独控制每个路由器组件（如VC队列、交叉MUX和输出锁存器）的电源供应。由于只有传输数据包的路由器组件被激活，片上网络的泄漏功率可以降低到接近最优的水平。但是，激活休眠组件需要一定的唤醒延迟，并且应用程序性能将会下降。在本文中，我们基于使用65nm工艺的电路模拟来估计每个组件的唤醒延迟。然后，我们提出了四种早期唤醒方法来克服唤醒延迟。从应用性能、面积和泄漏功率等方面对采用早唤醒方法的路由器进行了评价。因此，当我们假设1GHz工作时，它以4.3%的面积和4.0%的性能为代价，减少了78.9%的泄漏功率。
This paper proposes an ultra fine-grained run-time power gating of on-chip router, in which power supply to each router component (e.g., VC queue, crossbar MUX, and output latch) can be individually controlled in response to the applied workload.As only the router components which are just transferring a packet are activated, the leakage power of the on-chip network can be reduced to the near-optimal level.However, a certain amount of wakeup latency is required to activate the sleeping components, and the application performance will be degraded.In this paper, we estimate the wakeup latency for each component based on circuit simulations using a 65nm process.Then we propose four early wakeup methods to overcome the wakeup latency.The proposed router with the early wakeup methods is evaluated in terms of the application performance, area, and leakage power.As a result, it reduces the leakage power by 78.9%, at the expense of the 4.3% area and 4.0% performance when we assume a 1GHz operation.