Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe 2 Thin Film Transistors
Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe 2 Thin Film Transistors
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基于高性能双极双栅WSe 2 薄膜晶体管的级联逻辑门
DOI：
10.1021/acsnano.3c03932
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发表时间：
2023
期刊：
影响因子：
17.1
通讯作者：
Incorvia, Jean Anne
中科院分区：
文献类型：
--
作者：
Li, Xintong;Zhou, Peng;Hu, Xuan;Rivers, Ethan;Watanabe, Kenji;Taniguchi, Takashi;Akinwande, Deji;Friedman, Joseph S.;Incorvia, Jean Anne
基于低维材料（例如石墨烯、碳纳米管、黑磷和某些过渡金属二硫属化物（TMD））的双极双栅极晶体管实现了具有抑制的关态电流的可重构逻辑电路。这些电路实现了与互补金属氧化物半导体（CMOS）相同的逻辑输出，但晶体管数量更少，设计灵活性更大。主要的挑战在于这些具有静态CMOS类连接的逻辑门的可扩展性和功耗。在这篇文章中，高性能双极双栅晶体管的基础上，二硒化钨（WSe 2）的制造。在p型和n型输运中分别测得108和106的高开关比、100 ~ 300 fA的低关态电流、可忽略的迟滞和62和63 mV/dec的理想亚阈值摆幅。我们演示了使用双极TMD晶体管的可级联和级联逻辑门，具有最小的静态功耗，包括反相器、异或门、与非门、或非门以及由级联反相器制成的缓冲器。对控制栅和极性栅的特性进行了深入的研究。对逻辑门的噪声容限进行了测量和分析。大的噪声容限使得能够实现VT下降电路，这是一种具有减少的晶体管数量和简化的电路设计的逻辑类型。最后，定性地分析了用双栅器件构成的VT降等电路的速度性能。这项工作在双极性双栅TMD晶体管领域取得了进展，显示了它们在低功耗、高速和更灵活的逻辑电路中的潜力。
Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal–oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on–off ratio of 108and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.