Designing Virtual Network Functions for 100 GbE Network Using Multicore Processors
Designing Virtual Network Functions for 100 GbE Network Using Multicore Processors
复制标题
使用多核处理器设计 100 GbE 网络的虚拟网络功能
DOI：
--
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
Yan Luo
中科院分区：
文献类型：
--
作者：
Peilong Li;Xiaoban Wu;Yongyi Ran;Yan Luo
网络功能虚拟化（NFV）在设计基于软件的网络设备方面引入了极大的灵活性，以降低成本并加速网络运营商的服务部署。然而，随着100 GbE及以上高速网络的快速发展，如何在商用服务器上有效地设计虚拟网络功能（VNF）已成为一个具有挑战性的问题。虽然网络硬件和软件的进步已经通过硬件加速和内核/驱动优化促进了高速网络应用的设计，但是如何利用现有技术来设计优化的高性能VNF仍然是模糊的。在这项研究中，我们专注于四个广泛使用的VNF的设计和评估，涵盖网络交换/路由，访问控制，测量和安全领域，通过使用英特尔DPDK快速数据包I/O库支持的多核平台。我们描述了可用于实现100 Gbps网络速度的可编程NFV平台的多功能网络数据包接收和处理设计选项。通过大量的实验，我们评估了每个VNF的性能及其在丢包率，每个数据包的处理时间和每个数据包的延迟方面的设计选项。基于对收集到的数据的评估，我们提出了最佳的设计与给定的硬件资源，以维持线速率，同时达到最高水平的可编程性。
Network function virtualization (NFV) introduces great flexibility in designing software-based network appliances to reduce cost and accelerate service deployment for network operators. However, with the fast development of high speed network of 100 GbE and beyond, how to efficiently design virtual network functions (VNF) on commodity servers has become a challenging problem. Although the advances in network hardware and software have facilitated the design of high speed network applications with hardware acceleration and kernel/driver optimization, how to leverage the existing techniques to design optimized high-performance VNFs still remains vague. In this study, we focus on the design and evaluation of four widely used VNFs covering the domains of network switching/routing, access control, measurement and security, by using a multicore platform supported by Intel DPDK fast packet I/O library. We describe the versatile network packet receiving and processing design options available for implementing such a programmable NFV platform for 100 Gbps network speed. With extensive experiments, we evaluate the performance of the each VNF and its design options in terms of packet drop rate, processing time per packet and delay per packet. Based on the evaluation over the collected data, we propose the optimal design with the given hardware resources to sustain the line rate while achieving the highest level of programmability.