Improved Model-to-Hardware Correlation for Superconductor Integrated Circuits
Improved Model-to-Hardware Correlation for Superconductor Integrated Circuits
复制标题
改进的超导集成电路模型与硬件的相关性
DOI：
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发表时间：
2015
影响因子：
1.8
通讯作者：
D. Amparo
中科院分区：
文献类型：
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作者：
A. Inamdar;Jie Ren;D. Amparo
超导体（SC）集成电路具有几个固有的优点，包括低功率、高速度和分数通量量子灵敏度，其可以被利用来实现高速计算和射频域中的几个利基应用的区分性能。尽管SC电路具有几个优点，但由于电路良率低，其复杂度较高。限制成品率的关键因素之一是仿真模型与硬件相关性差。目前的SC电路仿真工具，如PSCAN是不足以模拟高电路的复杂性，并没有考虑到在制造过程中的变化。为了克服这一限制，我们开发了一个先进的基础设施，SC电路仿真，验证和模型到硬件的相关性的基础上的Cadence设计套件，特别是使用最先进的Spectre模拟器，支持高电路复杂性和蒙特卡罗模拟。改进的模型到硬件的相关性将带来几个好处，包括使电路能够扩展到更高的复杂性。通过新颖的诊断电路测量关键电路元件的统计分布，该诊断电路能够测量单个芯片上的多个实例并模仿实际电路中的布局特征。统计变化正在测量多个晶圆运行，并将被送入新的仿真基础设施，以实现更好地优化复杂的SC电路。此外，还设计了约瑟夫森传输线环形振荡器测试电路，并进行了测试，研究了每个结的延迟与特征电压Vc的关系。
Superconductor (SC) integrated circuits have several inherent advantages including low power, high speed, and fractional flux quantum sensitivity that can be exploited to achieve discriminating performance for several niche applications in the high-speed computing and radio frequency domain. Despite its several advantages, scaling of SC circuits to higher complexity has been inhibited by the poor circuit yield. One of the critical factors limiting the yield is the poor simulation model to hardware correlation. The current simulation tools for SC circuits such as PSCAN are inadequate to simulate high circuit complexity and do not account for the variations in the fabrication process. To overcome this limitation, we have developed an advanced infrastructure for SC circuit simulation, verification, and model-to-hardware correlation based on the Cadence design suite, particularly using the state-of-the-art Spectre simulator that supports high circuit complexity and Monte Carlo simulations. An improved model-to-hardware correlation will result in several benefits that include enabling circuit scaling to higher complexity. Statistical distributions for critical circuit elements are measured by novel diagnostic circuits that enable measuring multiple instances on a single chip and mimic layout features in actual circuits. Statistical variations are being measured over multiple wafer runs and will be fed into the new simulation infrastructure to achieve better optimization of a complex SC circuit. Furthermore, ring oscillator test circuits for Josephson transmission line have been designed and measured to study the delay per junction as a function of characteristic voltage Vc.