Generating synthetic benchmark circuits for evaluating CAD tools
Generating synthetic benchmark circuits for evaluating CAD tools
复制标题
生成用于评估 CAD 工具的综合基准电路
DOI：
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发表时间：
2000
期刊：
影响因子：
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通讯作者：
J. V. Campenhout
中科院分区：
文献类型：
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作者：
D. Stroobandt;P. Verplaetse;J. V. Campenhout
为了开发和评估用于数字电路的分区、布图规划、布局和布线的计算机辅助设计工具，需要大量具有合适特征参数的基准电路。由于缺乏可用于评估工具的工业基准电路，可以考虑实际生成合成电路。在本文中，我们扩展了基于图的基准生成方法，包括功能信息。使用用户指定的组件库，加上不引入组合循环的限制，现在将范围扩大到时序驱动和逻辑优化器应用程序。实验表明，所提出的扩展方法几乎不影响真实的电路与合成基准电路的特征Rent曲线和网度分布之间的相似性，所得电路比以前更真实.一个间接的验证验证，现有的分区程序具有可比的行为为真实的和合成电路。在合成基准的时间感知特性会计的问题进行了详细讨论，并包括扩展的建议。
For the development and evaluation of computer-aided design tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timing-aware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.