Redundancy identification and removal in combinational circuits
Redundancy identification and removal in combinational circuits
复制标题
组合电路中的冗余识别和消除
DOI：
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发表时间：
1994
期刊：
影响因子：
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通讯作者：
M. Harihara
中科院分区：
文献类型：
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作者：
P. R. Menon;Hitesh Ahuja;M. Harihara
识别和消除数字电路中的冗余对于提高其可测试性和减小其面积具有重要意义。通过对电路结构的分析，提出了一种识别和消除组合电路中冗余的方法。实验结果表明，该方法在执行时间上是相当有效的，但可能不能识别所有未检测到的故障。预计它将适合集成到逻辑综合系统中。它还可以用作测试模式生成程序或基于测试模式生成的冗余去除程序的预处理器。>；
Identification and removal of redundancy in digital circuits is important for improving their testability as well as reducing their area. This paper presents a method of identifying and removing redundancy in combinational circuits by analyzing circuit structure. Experimental results indicate that the method is quite efficient in execution time, but may not identify all undetectable faults. It is expected to be suitable for integration into a logic synthesis system. It can also be used as a preprocessor for a test pattern generation program or for a test pattern generation based redundancy removal program. >