Fabrication of surface ion traps with integrated current carrying wires enabling high magnetic field gradients
Fabrication of surface ion traps with integrated current carrying wires enabling high magnetic field gradients
复制标题
制造具有集成载流线的表面离子陷阱，可实现高磁场梯度
DOI：
10.1088/2058-9565/ac66fc
复制
发表时间：
2022
影响因子：
6.7
通讯作者：
Siegele-Brown M
中科院分区：
文献类型：
--
作者：
Siegele-Brown M
量子计算机的一个主要挑战是量子门的可扩展同时执行。在捕获离子量子计算机中解决这个问题的一种方法是基于静态磁场梯度和全局微波场的量子门的实现。在本文中，我们提出了制造表面离子阱集成铜载流导线嵌入在离子阱电极下方的基板内，能够产生高磁场梯度。在室温下测得的铜层薄层电阻为1.12 mΩ/sq，足以用于复杂设计，而不会在高电流下产生过度功耗，从而导致热失控。在40 K的温度下，薄层电阻下降到20.9 μΩ/sq，给出100的残余电阻比的下限。可以施加13 A的连续电流，在离子位置处产生144 T m− 1的模拟磁场梯度，对于我们设计中的特定反平行线对，该离子位置距离阱表面125 μm。
A major challenge for quantum computers is the scalable simultaneous execution of quantum gates. One approach to address this in trapped ion quantum computers is the implementation of quantum gates based on static magnetic field gradients and global microwave fields. In this paper, we present the fabrication of surface ion traps with integrated copper current carrying wires embedded inside the substrate below the ion trap electrodes, capable of generating high magnetic field gradients. The copper layer's measured sheet resistance of 1.12 mΩ/sq at room temperature is sufficiently low to incorporate complex designs, without excessive power dissipation at high currents causing a thermal runaway. At a temperature of 40 K the sheet resistance drops to 20.9 μΩ/sq giving a lower limit for the residual resistance ratio of 100. Continuous currents of 13 A can be applied, resulting in a simulated magnetic field gradient of 144 T m− 1 at the ion position, which is 125 μm from the trap surface for the particular anti-parallel wire pair in our design.