FPGA-Based Acceleration of Word2vec using OpenCL
FPGA-Based Acceleration of Word2vec using OpenCL
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DOI：
10.1109/iscas.2019.8702700
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发表时间：
2019-05
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通讯作者：
Taisuke Ono;T. Shoji;Hasitha Muthumala Waidyasooriya;M. Hariyama;Yuichiro Aoki;Yuki Kondoh;Yaoko Nakagawa
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作者：
Taisuke Ono;T. Shoji;Hasitha Muthumala Waidyasooriya;M. Hariyama;Yuichiro Aoki;Yuki Kondoh;Yaoko Nakagawa
Word2vec是一种词嵌入方法，它将词转换为向量，使得语义和语法相关的词在向量空间中彼此接近。由于数据量巨大，Word2vec的处理时间非常长。我们提出了一个高能效的基于FPGA的加速器设计使用OpenCL。与单核CPU实现相比，我们实现了13.4倍的速度提升，功耗仅为53W。与现有的基于GPU的高端加速器相比，所提出的基于FPGA的加速器具有最高的功率效率。
Word2vec is a word embedding method that converts words into vectors in such a way that the semantically and syntactically relevant words are close to each other in the vector space. The processing time of Word2vec is very large due to the huge data size. We propose a power efficient FPGA-based accelerator designed using OpenCL. We achieved 13.4 times speed-up compared to single-core CPU implementation with only 53W of power consumption. The proposed FPGA-based accelerator has the highest power-efficiency compared to existing top-end GPU-based accelerators.