Approximate MRAM: High-Performance and Power-Efficient Computing With MRAM Chips for Error-Tolerant Applications
Approximate MRAM: High-Performance and Power-Efficient Computing With MRAM Chips for Error-Tolerant Applications
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DOI：
10.1109/tc.2022.3174584
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发表时间：
2021-05
影响因子：
3.7
通讯作者：
F. Ferdaus;B. M. S. B. Talukder-B.-M.-S.-B.-Talukder-144641988;Md. Tauhidur Rahman
中科院分区：
文献类型：
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作者：
F. Ferdaus;B. M. S. B. Talukder-B.-M.-S.-B.-Talukder-144641988;Md. Tauhidur Rahman
近似计算（AC）利用固有的错误恢复能力，用于多媒体、计算机视觉、信号处理和机器学习等各个领域的许多大数据应用中，以提高系统性能和功耗。像许多其他近似电路和算法一样，内存子系统也可以用来提高性能和显著节省功耗。本文提出了一种高效和有效的系统方法来构建近似的非易失性磁阻RAM （MRAM）框架，使用消费者现成的（COTS） MRAM芯片。在所提出的方案中，通过操纵MRAM芯片的写入延迟，利用磁性隧道结（MTJs）固有的（内在/外在过程变化）随机开关行为，对存储器错误进行了广泛的实验表征。涉及抗错误图像压缩和机器学习应用的实验结果表明，所提出的AC框架提供了显着的性能改进，并证明MRAM写入能量平均降低47.5%，输出质量可以忽略不计或没有损失。
Approximate computing (AC) leverages the inherent error resilience and is used in many big-data applications from various domains such as multimedia, computer vision, signal processing, and machine learning to improve systems performance and power consumption. Like many other approximate circuits and algorithms, the memory subsystem can also be used to enhance performance and save power significantly. This paper proposes an efficient and effective systematic methodology to construct an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. In the proposed scheme, an extensive experimental characterization of memory errors is performed by manipulating the write latency of MRAM chips which exploits the inherent (intrinsic/extrinsic process variation) stochastic switching behavior of magnetic tunnel junctions (MTJs). The experimental results, involving error-resilient image compression and machine learning applications, reveal that the proposed AC framework provides a significant performance improvement and demonstrates a reduction in MRAM write energy of ${\sim }47.5\%$∼47.5% on average with negligible or no loss in output quality.