On testing of interconnect open defects in combinational logic circuits with stems of large fanout
On testing of interconnect open defects in combinational logic circuits with stems of large fanout
复制标题
大扇出组合逻辑电路互连开路缺陷的测试
DOI：
--
复制
发表时间：
2002
期刊：
影响因子：
--
通讯作者：
K. Kinoshita
中科院分区：
文献类型：
--
作者：
S. Reddy;I. Pomeranz;Huaxing Tang;S. Kajihara;K. Kinoshita
我们考虑具有大扇出节点的组合电路中互连开路缺陷的测试问题。我们提出了互连断开的门级故障模型。使用所提出的模型的互连开路故障的数量可能非常大，并且扇出大小呈指数级增长。我们描述了有效考虑大量开放故障的方法。这些方法包括隐式考虑开路故障的技术，以及使用有关驱动每个主输出的扇出分支的信息来减少故障列表。我们提出的实验结果证明，可以使用这些技术有效地对建模的开路故障进行故障模拟和测试生成。
We consider the problem of testing of interconnect open defects in combinational circuits with large fanout nodes. We propose a gate level fault model for interconnect opens. The number of interconnect open faults using the proposed model can be very large, being exponential in the fanout size. We describe methods to effectively consider the very large numbers of open faults. These methods include techniques for implicit consideration of open faults, and the use of information about fanout branches driving each primary output to reduce the list of faults. We present experimental results to demonstrate that fault simulation and test generation for the modeled open faults can be carried out efficiently using these techniques.