The need for a full-chip and package thermal model for thermally optimized IC designs
The need for a full-chip and package thermal model for thermally optimized IC designs
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DOI：
10.1145/1077603.1077662
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发表时间：
2005-08
期刊：
影响因子：
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通讯作者：
Wei Huang;Eric Humenay;K. Skadron;Mircea R. Stan
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文献类型：
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作者：
Wei Huang;Eric Humenay;K. Skadron;Mircea R. Stan
在早期设计阶段使用全芯片热模型对详细的芯片温度进行建模和分析对于发现和避免潜在的热危害非常重要。然而，在热模型中忽略封装细节的重要方面可能导致显著的温度估计误差。在本文中，我们讨论了现有的紧凑型热模型，模型的应用程序，无论是芯片和封装温度的细节。作为一个例子，热自洽泄漏功率计算的POWER4类微处理器设计。然后，我们证明了在热模型中包括详细的封装信息的重要性，考虑到热界面材料（TIM）的影响，其中胶水的模具散热器。事实上，需要详细的封装信息，以建立一个准确的紧凑的热模型意味着设计流程，其中芯片和封装级的紧凑的热模型作为一个方便的媒介，电路设计师，计算机架构师和封装设计师之间更富有成效的合作，导致早期和有效的评估不同的设计权衡，从热的角度来看，最佳设计。
Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally self-consistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip- and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view.