UpTime: Towards Flow-based In-Memory Computing with High Fault-Tolerance

UpTime: Towards Flow-based In-Memory Computing with High Fault-Tolerance
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DOI:
10.1109/dac56929.2023.10247692
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发表时间:
2023-07
期刊:
2023 60th ACM/IEEE Design Automation Conference (DAC)
影响因子:
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通讯作者:
Sven Thijssen;M. Rashed;Sumit Kumar Jha;Rickard Ewetz
Sven Thijssen;M. Rashed;Sumit Kumar Jha;Rickard Ewetz
中科院分区:
其他
文献类型:
--
作者:
Sven Thijssen;M. Rashed;Sumit Kumar Jha;Rickard Ewetz

文献摘要

相似文献

内存处理有望通过打破基于冯诺依曼的设计原则来加速数据密集型应用程序。基于流的计算是一种内存计算范式,在执行布尔逻辑方面显示出巨大的潜力。不幸的是,用于纳米级忆阻器交叉杆的不成熟制造工艺仍在与成品率挑战和运行时间缺陷作斗争,这可能使计算系统不起作用。更糟糕的是,以前没有研究过基于流的计算系统的容错性,这可能会限制整个范式的能力。在本文中,我们提出了UpTime框架,以提供对功能正确性和最大限度地提高基于流的计算系统的生命周期。该框架利用数据布局组织来减轻已知类型和位置的故障的错误。为了处理在运行时发生的缺陷,我们建议使用一个错误检测信号,可以用低开销进行评估。实验评估表明,UpTime框架能够保证平均15.24年的功能正确性。正常运行时间与停机时间之比为99.9992%。与使用最先进的写验证方案相比,所提出的错误信号分别降低了25%的功耗和6%的吞吐量。
Processing in-memory promises to accelerate data-intensive applications by breaking von-Neumann based design principles. Flow-based computing is an in-memory computing paradigm that has shown immense potential for executing Boolean logic. Unfortunately, the immature fabrication processes for nanoscale memristor crossbars still struggle with yield challenges and run-time defects, which may render the computing system non-functional. Even worse, no previous studies have investigated the fault-tolerance of flow-based computing systems, which could potentially limit the capabilities of the entire paradigm. In this paper, we propose the UpTime framework to provide guaranties on the functional correctness and to maximize the lifetime of flow-based computing systems. The framework utilizes data layout organization to mitigate errors from faults with known type and location. To handle defects occurring at run-time, we propose the use of an error detection signal that can be evaluated with low overhead. The experimental evaluation demonstrates that the UpTime framework is capable of guaranteeing functional correctness for an average of 15.24 years. The up-time to down-time ratio is 99.9992%. Compared with utilizing the state-of-the-art write-verify scheme, the proposed error signal reduces power consumption by 25% and increases throughput by 6%, respectively.