Fast scalable FPGA-based Network-on-Chip simulation models
Fast scalable FPGA-based Network-on-Chip simulation models
复制标题
基于快速可扩展 FPGA 的片上网络仿真模型
DOI：
10.1109/memcod.2011.5970513
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
Michael Papamichael
中科院分区：
文献类型：
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作者：
Michael Papamichael
本文介绍了一套两个基于FPGA的片上网络（NoC）仿真引擎，组成了2011年MEMOCODE设计竞赛在绝对性能类的获奖设计。这两个仿真引擎都是在Bluespec System Verilog（BSV）中开发的，并在Xilinx ML605 FPGA开发板上实现。对于较小的网络和较简单的路由器配置，采用直接映射方法，其中要模拟的网络直接在FPGA上实现。对于大型网络，由于FPGA资源限制，直接映射方法不可行，因此使用虚拟化时分复用方法。与提供的软件参考实现相比，我们的直接映射方法实现了三个数量级的加速，而我们的虚拟化时间复用方法实现了一到两个数量级的加速，这取决于网络和路由器配置。
This paper presents a set of two FPGA-based Network-on-Chip (NoC) simulation engines that composed the winning design of the 2011 MEMOCODE Design Contest in the absolute performance class. Both simulation engines were developed in Bluespec System Verilog (BSV) and were implemented on a Xilinx ML605 FPGA development board. For smaller networks and simpler router configurations a direct-mapped approach was employed, where the network to be simulated was directly implemented on the FPGA. For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time-multiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized time-multiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration.