A 14-bit 100-MS/s 85.2-dB SFDR pipelined ADC without calibration
A 14-bit 100-MS/s 85.2-dB SFDR pipelined ADC without calibration
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DOI：
10.1088/1674-4926/35/7/075006
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发表时间：
2014-07
影响因子：
5.1
通讯作者：
Nan Zhao;Hua Luo;Qi Wei;Huazhong Yang
中科院分区：
文献类型：
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作者：
Nan Zhao;Hua Luo;Qi Wei;Huazhong Yang
本文介绍了一种14位100 ms /s免校准流水线模数转换器（ADC）。为了在没有任何校准算法的情况下获得高线性度，我们仔细考虑了级分辨率和电路拓扑的选择。提出了一种带有额外时钟相位的可调整时序图，使剩余电压有更长的稳定时间并使其失真最小化。ADC采用低抖动的LVDS时钟输入缓冲器，以确保在高采样率下的良好性能。该ADC原型采用0.18 μm CMOS技术，在19.1 mhz输入信号下实现了85.2 dB的无杂散动态范围（SFDR）和63.4 dB的信噪比（SNDR），在2.0 v电源下功耗为412 mw，占地2.9 × 3.7mm2。
This paper describes a 14-bit 100-MS/s calibration-free pipelined analog-to-digital converter (ADC). Choices for stage resolution as well as circuit topology are carefully considered to obtain high linearity without any calibration algorithm. An adjusted timing diagram with an additional clock phase is proposed to give residue voltage more settling time and minimize its distortion. The ADC employs an LVDS clock input buffer with low-jitter consideration to ensure good performance at high sampling rate. Implemented in a 0.18-μm CMOS technology, the ADC prototype achieves a spurious free dynamic range (SFDR) of 85.2 dB and signal-to-noise-and-distortion ratio (SNDR) of 63.4 dB with a 19.1-MHz input signal, while consuming 412-mW power at 2.0-V supply and occupying an area of 2.9 × 3.7mm2.