Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process
Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process
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DOI：
10.1109/led.2005.845496
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发表时间：
2005-03
影响因子：
4.9
通讯作者：
J. Kang;H. Yu;C. Ren;X.P. Wang;M. Li;D. Chan;Y. Yeo;N. Sa;H. Yang;X.Y. Liu;R. Han;D. Kwong
中科院分区：
文献类型：
--
作者：
J. Kang;H. Yu;C. Ren;X.P. Wang;M. Li;D. Chan;Y. Yeo;N. Sa;H. Yang;X.Y. Liu;R. Han;D. Kwong
采用高温栅优先工艺制备了当量氧化层厚度(EOT)为0.95 nm的HFN-HFO/Sub2/栅极nMOSFET。器件具有亚1 nm的EOT、较高的电子有效迁移率(峰值/SPL sim/232 cm/sup2//V/SPL Middot/S)和在正的恒压应力下的良好的电稳定性。在亚1 nm HFN-HFO/Sub2/栅控nMOSFET中获得的这些改善的器件性能可以归因于在沉积HFN-HFO/Sub2/栅叠层后，由于950/SPL deg/C高温源/漏激活退火工艺，HfO/Sub2/层的界面和体陷阱电荷密度较低。
By using a high-temperature gate-first process, HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value /spl sim/232 cm/sup 2//V/spl middot/s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO/sub 2/-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO/sub 2/ layer due to the 950/spl deg/C high-temperature source/drain activation annealing process after deposition of the HfN--HfO/sub 2/ gate stack.