A Fractional- $N$ PLL With Space–Time Averaging for Quantization Noise Reduction
A Fractional- $N$ PLL With Space–Time Averaging for Quantization Noise Reduction
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具有时空平均功能的小数 $N$ PLL，可降低量化噪声
DOI：
10.1109/jssc.2019.2950154
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发表时间：
2020
影响因子：
5.4
通讯作者：
Nan Sun
中科院分区：
文献类型：
--
作者：
Yanlong Zhang;A. Sanyal;X. Yu;Xing Quan;Kailin Wen;Xiyuan Tang;Gang Jin;Li Geng;Nan Sun
本文提出了一种空时平均技术，它可以实现瞬时分数分频，从而可以显着降低量化误差的分数<inline-formula><tex-math notation="LaTeX">$N$</tex-math></inline-formula>锁相环（PLL）。空间平均可以通过使用并行运行的分频器阵列来实现。它们的不同分频比是通过使用分数<inline-formula><tex-math notation="LaTeX">$\Delta \Sigma $</tex-math></inline-formula>调制器（DSM）和动态元件匹配（DEM）块产生的。为了降低分频器的功耗，本文还提出了一种仅使用一个分频器和相位选择来实现空间平均的方法。一个原型的2.4 GHz的分数-<inline-formula><tex-math notation="LaTeX">$N$</tex-math></inline-formula>锁相环是在一个40 nm的CMOS工艺实现。测量结果表明，所提出的技术降低了10和21 dB的相位噪声在1和10 MHz的偏移，分别导致减少的综合均方根抖动从9.55到2.26 ps。
This article presents a space–time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL). Spatial averaging can be achieved by using an array of dividers running in parallel. Their different division ratios are generated by using a fractional <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator (DSM) and a dynamic element matching (DEM) block. To reduce the divider power, this article also proposes a way to achieve spatial averaging using only one divider and phase selection. A prototype 2.4-GHz fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL is implemented in a 40-nm CMOS process. Measurement results show that the proposed technique reduces the phase noise by 10 and 21 dB at the 1- and 10-MHz offset, respectively, leading to a reduction of the integrated rms jitter from 9.55 to 2.26 ps.