Test instruction set (TIS) for high level self-testing of CPU cores
Test instruction set (TIS) for high level self-testing of CPU cores
复制标题
用于 CPU 内核高级自测试的测试指令集 (TIS)
DOI：
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
Z. Navabi
中科院分区：
文献类型：
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作者：
S. Shamshiri;H. Esmaeilzadeh;Z. Navabi
TIS(测试指令集)是一种用于CPU内核自测试的指令级技术。该方法基于用测试指令增强CPU指令集。TIS用测试指令替换了大多数处理器中可用的NOP指令，因此可以在不影响性能的情况下完成在线测试。该方法适用于所有类型的处理器(单周期、多周期和流水线)的离线和在线(并发)测试。TIS适用于流水线体系结构，其中在依赖于数据或控制的指令之间插入一个或多个NOP指令(或停顿)。我们已经在流水线CPU核上实现了该测试方法，并使用了几个针对该流水线CPU的测试程序来说明该方法。文中还给出了故障覆盖结果，以验证TIS测试技术的有效性。
TIS (test instruction set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replaces the NOP instruction that is available in most processors with test instructions so that online testing can be done with no performance penalty. This method can be applied to both offline and online (concurrent) testing of all types of processors (single-cycle, multi-cycle and pipelined). TIS is appropriate for pipelined architectures in which one or many NOP instructions (or stalls) are inserted between instructions that are data or control dependent. We have implemented this test method on a pipelined CPU core and several test programs for this pipelined CPU are used to illustrate the method. Also fault coverage results are presented to demonstrate the effectiveness of the TIS test technique.