Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation
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DOI：
10.1109/tcad.2017.2778061
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发表时间：
2018-10
影响因子：
2.9
通讯作者：
Mengshuo Wang;Wenlong Lv;Fan Yang;Changhao Yan;W. Cai;Dian Zhou;Xuan Zeng
中科院分区：
文献类型：
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作者：
Mengshuo Wang;Wenlong Lv;Fan Yang;Changhao Yan;W. Cai;Dian Zhou;Xuan Zeng
本文提出了一种贝叶斯优化方法，用于模拟和 SRAM 电路的成品率优化。高斯过程 (GP) 回归用于预测具有不确定性信息的设计空间上的良率。在模型上构建预期改进获取函数，并使用基于效用的策略指导优化。这些技术作为一个整体，可以显着减少优化过程中昂贵的产量估计的数量。此外，GP 模型对受噪声干扰的目标的观测不确定性进行编码，从而能够对产量估计进行自适应控制。通过确保有前途的设计具有高估计精度，同时容忍低良率设计的较高变异性，所提出的方法可以显着降低良率估计的平均计算成本，而不会牺牲最终结果的准确性。实验结果表明，与最先进的良率优化方法相比，所提出的方法可以在不影响优化效果的情况下显着减少电路仿真次数。
In this paper, a Bayesian optimization approach is proposed for yield optimization of analog and SRAM circuits. Gaussian process (GP) regression is employed to predict the yield over the design space with uncertainty information. An expected improvement acquisition function is constructed over the model and guides the optimization with a utility-based strategy. These techniques, as a whole, can significantly reduce the number of expensive yield estimations during the optimization procedure. Furthermore, the GP model encodes the observation uncertainties of noise-corrupted objectives, which enables an adaptive control over yield estimations. By ensuring high estimation accuracies for promising designs while tolerating higher variabilities for low-yield ones, the proposed method can significantly cut down the average computational cost of yield estimations without surrendering the accuracy of the final result. Experimental results show that, compared with the state-of-the-art yield optimization approaches, the proposed method can significantly reduce the number of circuit simulations without compromising optimization efficacy.