Fabrication process and failure analysis for robust quantum dots in silicon
Fabrication process and failure analysis for robust quantum dots in silicon
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DOI：
10.1088/1361-6528/abb559
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发表时间：
2020-12-11
期刊：
影响因子：
3.5
通讯作者：
Eriksson, M. A.
中科院分区：
文献类型：
--
作者：
Dodson, J. P.;Holman, Nathan;Eriksson, M. A.
我们提出了一种改进的 Si/SiGe 异质结构上重叠铝栅极量子点器件的制造工艺，该工艺结合了低温栅极间氧化、栅极氧化物热退火、片上静电放电 (ESD) 保护以及考虑热预算的优化互连工艺。该工艺减少了栅极到栅极的泄漏、ESD 造成的损坏、铝的去湿以及器件互连中不需要的合金的形成。此外，横截面扫描透射电子显微镜（STEM）图像阐明了随着器件几何形状的变化，有源区域中的栅电极形态。我们表明，重叠的铝栅极层均匀地符合其下方的拓扑，与栅极几何形状无关，并识别栅极几何形状中的关键尺寸，其中图案转移变得不理想，从而导致器件故障。
We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temperature inter-gate oxidation, thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum and formation of undesired alloys in device interconnects. Additionally, cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphology in the active region as device geometry is varied. We show that overlapping aluminum gate layers homogeneously conform to the topology beneath them, independent of gate geometry and identify critical dimensions in the gate geometry where pattern transfer becomes non-ideal, causing device failure.