FPGA Implementation of Gated Clock based Globally Asynchronous Locally Synchronous Wrapper Circuits
FPGA Implementation of Gated Clock based Globally Asynchronous Locally Synchronous Wrapper Circuits
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基于门控时钟的全局异步局部同步封装电路的 FPGA 实现
DOI：
10.1109/isscs.2007.4292699
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
Hossein Pedram
中科院分区：
文献类型：
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作者：
Esmaeil Amini;M. Najibi;Zahra Jeddi;Hossein Pedram
本文的重点是在商用fpga上对基于可调时钟和门控时钟的GALS系统进行原型设计。基于可调时钟的GLAS系统使用片上时钟发生器产生可调时钟脉冲，而基于门控时钟的GALS系统使用片外时钟信号，该信号在需要异步数据通信时进行门控。这两种设计方案在维特比误差检测与校正电路上进行了验证。虽然在合理的GALS包装中使用片上可调时钟会导致鲁棒性和性能之间的权衡，但已经证明使用门控时钟方案可以提高性能和鲁棒性。此外，基于门控时钟的GALS Viterbi的面积开销小于基于可调时钟的GALS Viterbi的面积开销。
This paper focuses on prototyping pausible and gated clock based GALS systems on commercial FPGAs. Pausible clock based GLAS systems use an on-chip clock generator to generate pausible clock pulses whereas gated clock based GALS systems use an off-chip clock signal that is gated whenever asynchronous data communication is required. These two design schemes have been examined on Viterbi error detection and correction circuit. While using on-chip pausible clocks in plausible GALS wrappers leads to a tradeoff between robustness and performance, it has been shown that both performance and robustness can be improved by using the gated clock scheme. In addition, the area overhead of gated clock based GALS Viterbi was less than the area overhead of pausible clock based GALS Viterbi.