Through Silicon Via Reliability
Through Silicon Via Reliability
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DOI：
10.1109/tdmr.2012.2189212
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发表时间：
2012-02
影响因子：
2
通讯作者：
C. Cassidy;J. Kraft;S. Carniello;F. Roger;H. Ceric;A. Singulani;E. Langer;F. Schrank
中科院分区：
文献类型：
--
作者：
C. Cassidy;J. Kraft;S. Carniello;F. Roger;H. Ceric;A. Singulani;E. Langer;F. Schrank
通过利用贯穿整个硅衬底的互连（称为硅通孔，TSV），可以实现不同半导体技术的垂直集成。鉴于此类结构相关的特定制造技术、几何形状和潜在失效模式，TSV为可靠性评估提供了一个有趣的案例研究。介绍了一种特定的TSV技术，并讨论了可靠性评估的关键参数，如残余应力、电阻、泄漏和介质击穿。给出了可靠性数据，包括TSV参数作为各种加速寿命应力测试的函数的特性，以及对TSV制造缺陷的密度和影响的评估。所呈现的数据表明，虽然TSV本身相当坚固，但潜在的制造缺陷对长期可靠性构成重大风险。讨论了筛选方法、缺陷模式、失效分析方法、工艺改进以及相应改进的缺陷密度结果。这些结果被认为与新型3D集成工艺技术的开发和可靠性相关。
Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage, and dielectric breakdown, are discussed. Reliability data are presented, including the characterization of TSV parameters as a function of various accelerated lifetime stress tests, as well as assessments of the density and impact of TSV manufacturing defects. The presented data demonstrate that while the TSV is inherently quite robust, latent manufacturing defects pose a significant risk to long-term reliability. Screening methodologies, defect modes, failure analysis methods, process improvement, and correspondingly improved defect density results are discussed. The results are considered pertinent to the development and reliability of novel 3-D integrated process technologies.