IBM PowerPC 440 FPU with complex-arithmetic extensions
IBM PowerPC 440 FPU with complex-arithmetic extensions
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具有复杂算术扩展的 IBM PowerPC 440 FPU
DOI：
10.1147/rd.492.0249
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
Charles D. Wait
中科院分区：
文献类型：
--
作者：
Charles D. Wait
具有复杂算术扩展的PowerPC®440浮点单元（FPU）是一种嵌入式专用集成电路（ASIC）核心，旨在与Blue Gene®/L计算芯片上的IBM PowerPC 440处理器核心一起使用。FPU核心实现了来自PowerPC Architecture™的浮点指令集和为帮助进行矩阵和复杂算术运算而创建的浮点指令扩展。FPU指令扩展定义了双精度操作，这些操作主要是单指令多数据（SIMD），需要两个（主和辅助）算术管道和浮点寄存器文件。然而，为了帮助复杂的算术例程，一些FPU扩展实际上在算术管道中执行不同的（但密切相关的）操作。FPU核心实现主和辅助算术数据路径之间的操作数交叉栏，以使每个管道操作数能够从主或辅助寄存器文件访问。PowerPC 440处理器核心提供了128位存储总线和同时发出算术指令与存储指令，允许FPU核心充分利用并行算术管道。
The PowerPC® 440 floating-point unit (FPU) with complex-arithmetic extensions is an embedded application-specific integrated circuit (ASIC) core designed to be used with the IBM PowerPC 440 processor core on the Blue Gene®/L compute chip. The FPU core implements the floating-point instruction set from the PowerPC Architecture™ and the floating-point instruction extensions created to aid in matrix and complex-arithmetic operations. The FPU instruction extensions define double-precision operations that are primarily single-instruction multiple-data (SIMD) and require two (primary and secondary) arithmetic pipelines and floating-point register files. However, to aid complex-arithmetic routines, some FPU extensions actually perform different (yet closely related) operations while executing in the arithmetic pipelines. The FPU core implements an operand crossbar between the primary and secondary arithmetic datapaths to enable each pipeline operand access from the primary or secondary register file. The PowerPC 440 processor core provides 128-bit storage buses and simultaneous issue of an arithmetic instruction with a storage instruction, allowing the FPU core to fully utilize the parallel arithmetic pipes.