A JTAG based 3D DfT architecture using automatic die detection
A JTAG based 3D DfT architecture using automatic die detection
复制标题
使用自动芯片检测的基于 JTAG 的 3D DfT 架构
作者：
Yassine Fkih;P. Vivet;B. Rouzeyre;M. Flottes;G. Di Natale
基于硅通孔（TSV）的3D叠层集成电路具有高性能和小尺寸等优点。然而，这些电路存在许多测试问题，包括所有3D制造级别的测试：焊接前、焊接中和焊接后级别。在本文中，我们提出了一种自动芯片检测机制，能够检测上下芯片的存在，并在JTAG的3D测试架构中集成。3D芯片检测器允许优化整个3D测试架构：使其在所有堆叠级别都可用，而无需配置步骤。本文还介绍了所提出的具有管芯检测器的测试架构的综合结果。
3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues including the test at all 3D manufacturing levels: pre, mid, and post bond levels. In this paper we propose an automatic die-detection mechanism able to detect the presence of upper and lower dies, and its integration within a JTAG based 3D test architecture. 3D die-detectors permit the optimization of the overall 3D test architecture: making it usable at all stacking levels without requiring a configuration step. This paper presents also synthesis results of the proposed test architecture with die-detectors.