Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks
Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks
复制标题
使用 XY 方向连接子图分区和多个测试时钟的片上网络测试调度
DOI：
10.1007/s10836-016-5565-5
复制
发表时间：
2016-02-01
影响因子：
0.9
通讯作者：
Jia, Mengyi
中科院分区：
文献类型：
--
作者：
Hu, Cong;Li, Zhi;Jia, Mengyi
在片上网络（NoC）系统测试中，复用片上功能互连线作为测试访问机制（TAM）是一个很有吸引力的研究方向。然而，在NoC复用的方法论TAM中，NoC测试的影响因素显著增加。为了进一步减少测试时间并显示出比其他工作的显着收益，我们提出了XY方向连通子图分区（XYCSP）的方法来消除路径冲突之前，测试，并同时确定测试访问点的位置。然后，我们提出了一个多测试时钟的策略，桥接片上网络通道带宽和核心测试包装器带宽之间的差距。该算法采用自适应概率门量子进化算法（APGQEA）策略，融合了自适应策略和面向多变量技术，实现了对解空间的快速探索和利用.此外，还考虑了功率约束。ITC'02基准测试的实验结果表明，该方案可以实现更短的测试时间相比，以前的工作。
It is attractive to reuse the on-chip functional interconnects as test access mechanism (TAM) in network-on-chip (NoC) system testing. However, in the methodology of NoC-reuse as TAM, the influence factors in NoC testing significantly increased. To further reduce test time and show significant gains over other work, we propose XY-direction connected subgraph partition (XYCSP) approach to eliminate the path conflicts before testing, and concurrently determine the position of test access points. We then present a multiple test clock strategy to bridge the gap between the NoC channel bandwidth and the core test wrapper bandwidth. With the help of adaptive probability gate quantum-inspired evolutionary algorithm (APGQEA) strategy, which blends adaptive strategy and multi-nary oriented techniques, the proposed NoC test scheduling algorithm permits quick exploration and exploitation of the solution space. Moreover, power constraints are also taken into account. Experimental results for the ITC’02 benchmarks show that the proposed scheme can achieve shorter test time compared to prior works.