13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS
13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS
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DOI：
10.1109/isscc.2014.6757418
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发表时间：
2014-03
期刊：
影响因子：
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通讯作者：
Bharan Giridhar;N. Pinckney;D. Sylvester;D. Blaauw
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文献类型：
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作者：
Bharan Giridhar;N. Pinckney;D. Sylvester;D. Blaauw
这项工作提出了一种面积有效和变化容限的小信号差分检测（VTS）方案，该方案修改了传统的SA电路，包括：1）用于动态自动调零偏移补偿的结构，2）通过将SA反相器对重新配置为放大器来对ADC差分进行预放大，以及3）通过将SA返回到其常规交叉耦合配置来锁存放大的电压差分。该方法被证明可以在没有面积开销的情况下，在等感测时间上提高传统感测的SA鲁棒性（图13.7.1）。相反，感测时间可以在等鲁棒性和面积下减少。对28 nm CMOS测试芯片的测量表明，等面积VTS方案在等鲁棒性（<0.3%故障率）下将失调噪声容限提高了-1.2 Vth或将检测速度提高了42%。
This work presents an area-efficient and variation-tolerant small-signal differential sensing (VTS) scheme that modifies the conventional SA circuit to include: 1) a structure for on-the-fly, auto-zeroing offset compensation, 2) pre-amplification of bitline differential by reconfiguring the SA inverter pair as amplifiers, and 3) latching of the amplified voltage differential by returning the SA to its conventional cross-coupled configuration. The approach is demonstrated to improve SA robustness over conventional sensing at isosensing time without area overhead (Fig. 13.7.1). Conversely, sensing time can be reduced at iso-robustness and area. Measurements of a 28nm CMOS test chip show that an iso-area VTS scheme improves offset noise tolerance by -1.2σVth or sensing speed by up to 42% at iso-robustness (<;0.3% failure rate).