Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures
Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures
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DOI：
10.1109/isca52012.2021.00041
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发表时间：
2021-06
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通讯作者：
Ajay Brahmakshatriya;Emily Furst;Victor A. Ying;Claire Hsu;Changwan Hong;Max Ruttenberg;Yunming Zhang-Yunming
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作者：
Ajay Brahmakshatriya;Emily Furst;Victor A. Ying;Claire Hsu;Changwan Hong;Max Ruttenberg;Yunming Zhang-Yunming
我们生活在一个新的寒武纪硬件设备爆炸。传统处理器扩展的终结推动了研究和行业实践探索新一代方法。架构设计的旧DNA，包括向量、线程、共享或私有存储器、一致性或消息传递、执行力或冯·诺依曼，以新的令人兴奋的方式混合在一起。每个新的体系结构都公开了唯一的硬件级API。性能和能源效率主要取决于程序如何使用这些API。一种方法是为每个新的硬件架构和应用程序域实现自定义库。一个更具可扩展性的方法是利用一个可移植的编译器基础设施，定制的应用程序域，使它很容易生成高效的代码，为不同的一组架构，以最小的porting effortes.We提出了统一的GraphIt编译器框架（UGC），这正是图应用程序。UGC通过将独立于架构的算法与特定于架构的调度和后端解耦，以合理的努力实现可移植性。我们引入了一个新的特定于域的中间表示，GraphIR，这是这种解耦的关键。GraphIR对硬件特定代码生成所需的高级算法和优化信息进行编码，从而可以轻松地为不同的架构开发不同的后端（GraphVM），包括CPU，GPU和下一代硬件，如Swarm和HammerBlade众核。我们还构建了调度语言扩展，使其易于公开优化决策，如负载平衡策略，局部阻塞和其他数据结构选择。我们在这4种不同的架构上对5种算法和10种输入图进行了UGC评估，并表明UGC可以实现优化，与程序员生成的直接实现相比，可以提供高达53倍的加速比。
We live in a new Cambrian Explosion of hardware devices. The end of conventional processor scaling has driven research and industry practice to explore a new generation of approaches. The old DNA of architecture design, including vectors, threads, shared or private memories, coherence or message passing, dataflow or von Neumann execution, are hybridized together in new and exciting ways. Each new architecture exposes a unique hardware-level API. Performance and energy efficiency are critically dependent on how well programs can use these APIs. One approach is to implement custom libraries for each new hardware architecture and application domain. A more scalable approach is to utilize a portable compiler infrastructure tailored to the application domain that makes it easy to generate efficient code for a diverse set of architectures with minimal porting effort.We propose the Unified GraphIt Compiler framework (UGC), which does exactly this for graph applications. UGC achieves portability with reasonable effort by decoupling the architecture-independent algorithm from the architecture-specific schedules and backends. We introduce a new domain-specific intermediate representation, GraphIR, that is key to this decoupling. GraphIR encodes high-level algorithm and optimization information needed for hardware-specific code generation, making it easy to develop different backends (GraphVMs) for diverse architectures, including CPUs, GPUs, and next-generation hardware such as Swarm and the HammerBlade manycore. We also build scheduling language extensions that make it easy to expose optimization decisions like load balancing strategies, blocking for locality, and other data structure choices. We evaluate UGC on five algorithms and 10 input graphs on these 4 distinct architectures and show that UGC enables implementing optimizations that can provide up to 53× speedup over programmer-generated straightforward implementations.