Temporally synchronized emulation of devices with simulation of networks
Temporally synchronized emulation of devices with simulation of networks
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DOI：
10.1145/3518997.3531020
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发表时间：
2022-06
期刊：
影响因子：
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通讯作者：
Vignesh Babu;D. Nicol
中科院分区：
文献类型：
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作者：
Vignesh Babu;D. Nicol
我们描述了一个平台，该平台使用仿真设备的临时集成联合仿真和连接它们的网络仿真，用于性能评估和弹性评估等活动。在我们的方法中，所有仿真和模拟的组件都与虚拟时钟时间同步。我们提出并研究了一种利用编译器分析来增强仿真代码和逻辑的方法，以精确地跟踪执行路径的指令级。这与一种机制相结合，该机制根据执行指令的顺序为每个执行突发分配虚拟时间。仿真组件和仿真组件之间的同步开销通过基于编译器的“前瞻”识别来减少，“前瞻”识别模拟执行的时间点，在此期间可以预测进程独立于任何其他进程。通过评估，我们表明我们的方法能够快速和可重复地执行共同模拟模型。
We describe a platform that uses temporally integrated co-simulation of emulated devices and simulation of networks that connect them, for activities such as performance evaluation and resilience assessment. In our approach all emulated and simulated components are time-synchronized to a virtual clock. We propose and study an approach which uses compiler analysis to augment emulated code with logic for precise instruction level tracking of execution paths. This is combined with a mechanism to ascribe virtual time for each execution burst based on the sequence of executed instructions. The overhead of synchronization between emulated components and simulated components is reduced by compiler-based identification of “lookahead”, which identifies epochs of emulated execution during which a process can be predicted to act independently of any other. Through evaluations, we show that our approach enables fast and repeatable execution of co-simulated models.