Low-Power 4 × 4-Bit Array Two-Phase Clocked Adiabatic Static CMOS Logic Multiplier
Low-Power 4 × 4-Bit Array Two-Phase Clocked Adiabatic Static CMOS Logic Multiplier
复制标题
低功耗 4 × 4 位阵列两相时钟绝热静态 CMOS 逻辑乘法器
DOI：
--
复制
发表时间：
2010
期刊：
影响因子：
--
通讯作者：
T. Sekine
中科院分区：
文献类型：
--
作者：
Nazrul Anuar;Yasuhiro Takahashi;T. Sekine
本文给出了一种采用1.2µm标准CMOS技术的4 × 4位阵列2PASCL乘法器的仿真结果及其版图设计。从SPICE模拟来看，在1到12 MHz的过渡频率下，4 × 4位阵列2PASCL乘法器的功耗比静态CMOS最大降低57%。对流过2PASCL和CMOS晶体管的电流进行了观察。从仿真结果来看，2PASCL技术可以有利地应用于工作在低频率下的低功耗数字设备，如射频识别（rfid）、智能卡和传感器。
—This paper presents the simulation results of a 4 × 4-bit array 2PASCL multiplier and its layout design using 1.2 µ m standard CMOS technology. From the SPICE simulation, at transition frequencies of 1 to 12 MHz, 4 × 4-bit array 2PASCL multiplier shows a maximum of 57 % reduction in power dissipation to that of a static CMOS. Observations on the current that flows through the transistors in 2PASCL and CMOS are also presented. From the simulation results, 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.