A New Extension Method of Retention Time for Memory Cell on Dynamic Random Access Memory
A New Extension Method of Retention Time for Memory Cell on Dynamic Random Access Memory
复制标题
动态随机存储器存储单元保留时间延长新方法
DOI：
10.1016/j.vlsi.2013.10.004
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Y. Riho and K. Nakazato
中科院分区：
文献类型：
--
作者：
Leonel Aguilar;Maddegedara Lalith;Muneo Hori;Tsuyoshi Ichimura;and Seizo Tanaka;Y. Riho and K. Nakazato
已经对动态随机存取存储器(DRAM)提出了要求，不仅要具有更高的存储容量和数据传输速度，而且还要降低操作和待机电流。当系统使用DRAM时，由于其数据保留时间的限制，刷新操作是必要的：DRAM的每一位都作为电荷量存储在存储电容器中。刷新操作的功耗与存储器容量成比例增加。提出了一种新的方法，通过有效地延长存储单元的保留时间，在不需要满存储容量的情况下动态降低刷新功耗。从1个单元/位到2N个单元/位的转换减少了存储单元之间的保持时间的变化。该方法将扰动频率及其功耗降低了两个数量级。转换本身可以从DRAM阵列电路的结构非常简单地实现，在全阵列访问模式的情况下保持所有常规功能和操作。
Demands have been placed on a dynamic random access memory (DRAM) to not only have increased memory capacity and data transfer speed but also have reduced operating and standby currents. When a system uses a DRAM, a refresh operation is necessary because of its data retention time restriction: each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to the memory capacity. A new method is proposed to reduce refresh power consumption dynamically when the full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2Ncells/bit reduces the variation of retention time among memory cells. This method reduces the frequency of disturbance and its power consumption by two orders of magnitude. The conversion itself can be realized very simply from the structure of the DRAM array circuit, maintaining all conventional functions and operations in case of the full array access mode.