Automatic creation of domain-specific reconfigurable CPLDs for SOC
Automatic creation of domain-specific reconfigurable CPLDs for SOC
复制标题
为 SOC 自动创建特定领域的可重配置 CPLD
DOI：
--
复制
发表时间：
2005
期刊：
影响因子：
--
通讯作者：
S. Hauck
中科院分区：
文献类型：
--
作者：
M. Holland;S. Hauck
许多片上系统器件将受益于在硅管芯上包含可重编程逻辑，因为它可以增加通用计算能力，提供运行时可重配置性，甚至用于制造后修改。此外，通过将逻辑迎合SoC域，可以在当前更一般的可重配置结构上实现额外的面积和延迟增益。本文介绍了自动创建域特定的CPLD的SoC，包括一个架构生成器，找到合适的架构和布局生成器，用于创建高效的布局的工具。通过定制CPLD的域，他们所支持的，我们提供的结果，击败代表性的固定架构的5.6/SPL倍/到11.9/SPL倍/平均面积延迟产品。
Many system-on-a-chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurability, or even be used for post-fabrication modifications. Also, by catering the logic to the SoC domain, additional area and delay gains can be achieved over current, more general reconfigurable fabrics. This paper presents tools that automate the creation of domain-specific CPLDs for SoC, including an architecture generator for finding appropriate architectures and a layout generator for creating efficient layouts. By tailoring CPLDs to the domains that they are supporting, we provide results that beat representative fixed architectures by 5.6/spl times/ to 11.9/spl times/ on average in terms of area-delay product.