Quantifying the Capacity Limitations of Hardware Transactional Memory
Quantifying the Capacity Limitations of Hardware Transactional Memory
复制标题
量化硬件事务内存的容量限制
DOI：
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复制
发表时间：
2015
期刊：
影响因子：
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通讯作者：
N. Shavit
中科院分区：
文献类型：
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作者：
William Hasenplaugh;Andrew Nguyen;N. Shavit
硬件事务通过利用已经快速、自动和并行的现有高速缓存一致性机制的能力，提供了优于软件实现的性能优势。然而，上级性能的来源也是其弱点的根源：当工作集超过底层硬件的容量时，硬件事务的现有实现会中止。在我们将这种新兴技术纳入高性能并发数据结构之前，有必要研究这些容量限制，以便更好地告知程序员他们的能力和局限性。本文提供了第一个全面的实证研究的“容量信封”的HTM在英特尔的Haswell和IBM的Power8架构，提供了我们认为是一个非常需要的理解，在何种程度上可以使用这些系统来取代锁。
Hardware transactions offer a performance advantage over software implementations by harnessing the power of existing cache coherence mechanisms which are already fast, automatic, and parallel. The source of superior performance, however, is also the root of their weakness: existing implementations of hardware transactions abort when the working set exceeds the capacity of the underlying hardware. Before we can incorporate this nascent technology into high-performing concurrent data structures, it is necessary to investigate these capacity constraints in order to better inform programmers of their abilities and limitations. This paper provides the first comprehensive empirical study of the “capacity envelope” of HTM in Intel’s Haswell and IBM’s Power8 architectures, providing what we believe is a much needed understanding of the extent to which one can use these systems to replace locks.
利用主内存数据库中的硬件事务内存
DOI：
10.1109/icde.2014.6816683
发表时间：
2014
期刊：
2014 IEEE 30th International Conference on Data Engineering
影响因子：
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作者：
V. Leis;A. Kemper;T. Neumann
通讯作者：
T. Neumann