Timing-Abstract Circuit Design in Transaction-Level Verilog
Timing-Abstract Circuit Design in Transaction-Level Verilog
复制标题
事务级 Verilog 中的时序抽象电路设计
DOI：
10.1109/iccd.2017.91
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
Steven F. Hoover
中科院分区：
文献类型：
--
作者：
Steven F. Hoover
鉴于现代集成电路的复杂性，设计重用是必不可少的，但是当前的硬件说明语言无法充分解决许多类别设计的重用挑战。例如，处理器核心是由周期级相互作用来塑造的，并利用此类设计进入具有不同正时约束的环境，需要重新安排，重新定位和微体系结构变化。在寄存器转移级别进行这些更改需要重大重写。需要抽象，但是SystemC和OpenCL的抽象更适合于松散耦合的微体系式相互作用。提出了一种定时建模方法，该方法将行为和时机的关注点分开。在管道的上下文中指定了提时 - 提取行为，并且管道内的逻辑被分配给管道阶段，以实现细节。顺序元素是由管道规范中的工具生成的。逻辑可以轻松地重新安排，而不会引入功能错误的风险，因此设计和验证工作可以集中于将设计重新定为具有不同正时约束的上下文所需的行为更改。作为次要好处，指定寄存器 - 转移级的细节所需的源代码要少得多。
Given the complexity of modern integrated circuits, design reuse is essential, but current hardware description languages do not adequately address reuse challenges for many classes of design. Processor cores, as an example, are shaped by cycle-level interactions, and leveraging such designs into environments with different timing constraints requires retiming, repipelining, and microarchitectural changes. Making these changes at the register-transfer level requires significant rewriting. Abstraction is needed, but the abstractions of SystemC and OpenCL are more appropriate for loosely-coupled microarchitectural interactions. A timing-abstract modeling approach is presented that separates the concerns of behavior and timing. Timing-abstract behavior is specified within the context of pipelines, and logic within pipelines is assigned to pipeline stages as a matter of implementation detail. Sequential elements are generated by tools from the pipelined specification. Logic can be retimed easily, without the risk of introducing functional bugs, so design and verification effort can be focused on the behavioral changes required to retarget a design to a context with different timing constraints. As a secondary benefit, significantly less source code is required to specify register-transfer-level detail.