High voltage BiCDMOS technology on bonded 2 /spl mu/m SOI integrating vertical npn pnp, 60 V-LDMOS and MPU, capable of 200/spl deg/C operation
High voltage BiCDMOS technology on bonded 2 /spl mu/m SOI integrating vertical npn pnp, 60 V-LDMOS and MPU, capable of 200/spl deg/C operation
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采用粘合 2 /spl mu/m SOI 的高压 BiCDMOS 技术，集成垂直 npn pnp、60 V-LDMOS 和 MPU，能够在 200/spl deg/C 温度下运行
DOI：
10.1109/iedm.1995.499377
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发表时间：
1995
期刊：
影响因子：
--
通讯作者：
A. Nakagawa
中科院分区：
文献类型：
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作者：
H. Funaki;Y. Yamaguchi;Y. Kawaguchi;Y. Terazaki;H. Mochizuki;A. Nakagawa
在2 /spl μ/m厚的SOI上研制了沟槽隔离60 V BiCDMOS工艺，能够集成60 V低导通电阻横向DMOS、垂直NPN和PNP以及MPU。200/spl deg/C高温运行已得到证实。该工艺与传统的0.8 /spl μ/m规则CMOS工艺完全兼容，并且能够将任何现有的MPU、逻辑和模拟电路库与60 V DMOS H桥集成在一起。
Trench isolated 60 V BiCDMOS processes on bonded 2 /spl mu/m thick SOI, capable of integrating 60 V low on-resistance lateral DMOS, vertical npn and pnp, and an MPU have been developed. 200/spl deg/C high temperature operation has been demonstrated. The processes are completely compatible with the conventional 0.8 /spl mu/m rule CMOS processes, and are capable of integrating any existing library of MPUs, logic and analog circuits together with 6O V DMOS H bridges.