Scaling of pneumatic digital logic circuits
Scaling of pneumatic digital logic circuits
复制标题
DOI：
10.1039/c4lc01048e
复制
发表时间：
2015-01-01
期刊：
影响因子：
6.1
通讯作者：
Hui, Elliot E.
中科院分区：
文献类型：
--
作者：
Duncan, Philip N.;Ahrar, Siavash;Hui, Elliot E.
将集成电路缩小到更小的尺寸对于实现增加的系统复杂性和速度是至关重要的。到目前为止，由气动微流体部件组成的数字逻辑电路被限制在2-4门cm（-2）的电路密度，限制了可以实现的数字系统的复杂性。我们探索了使用精密加工技术来减小气动阀和电阻器的尺寸，并实现更准确和有效的端口和过孔布置。通过这种方式，我们获得了一个数量级的电路密度增加，达到高达36门cm（-2）。在360 mm（2）的面积上实现了由96个门组成的12位二进制计数器电路。体积的缩小，也带来了速度的数量级提升。1/3级环形振荡器的频率从2.6 Hz增加到22.1 Hz，二进制计数器的最大时钟频率从1/3 Hz增加到6 Hz。
The scaling of integrated circuits to smaller dimensions is critical for achieving increased system complexity and speed. Digital logic circuits composed of pneumatic microfluidic components have to this point been limited to a circuit density of 2-4 gates cm(-2), constraining the complexity of the digital systems that can be achieved. We explored the use of precision machining techniques to reduce the size of pneumatic valves and resistors, and to achieve more accurate and efficient placement of ports and vias. In this way, we attained an order of magnitude increase in circuit density, reaching as high as 36 gates cm(-2). A 12-bit binary counter circuit composed of 96 gates was realized in an area of 360 mm(2). The reduction in size also brought an order of magnitude increase in speed. The frequency of a 13-stage ring oscillator increased from 2.6 Hz to 22.1 Hz, and the maximum clock frequency of a binary counter increased from 1/3 Hz to 6 Hz.