Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders
复制标题
经济高效、高吞吐量 LDPC 解码器的分析和设计
DOI：
--
复制
发表时间：
2017
影响因子：
2.8
通讯作者：
O. Boncalo
中科院分区：
文献类型：
--
作者：
T. T. Nguyen;V. Savin;K. Le;D. Declercq;Fakhreddine Ghaffari;O. Boncalo
本文介绍了一种低密度奇偶校验（LDPC）解码器的低成本、高吞吐量硬件设计的新方法。所提出的方法，称为非满射有限字母迭代解码器（NS-FAIDs），利用了消息传递LDPC解码器对交换消息计算不准确性的鲁棒性，并且为先前在文献中提出的几种设计提供了统一的框架。NS-FAIDs对规则和不规则LDPC码进行了密度演化优化，并在硬件复杂度和解码性能之间提供了不同的权衡。同时提出了两种针对高吞吐量应用的硬件架构，集成了最小和（MS）和NS-FAID解码内核。基于65纳米CMOS技术的ASIC合成后实现结果表明，NS-FAIDs的吞吐量面积比显著提高，比MS解码器提高58.75%，纠错性能甚至更好或仅略有下降。
This paper introduces a new approach to cost-effective, high-throughput hardware designs for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective finite alphabet iterative decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different tradeoffs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65-nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.