IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor
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DOI：
10.1007/978-3-540-92990-1_11
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发表时间：
2008-12
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通讯作者：
Jörg Mische;S. Uhrig;Florian Kluge;T. Ungerer
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作者：
Jörg Mische;S. Uhrig;Florian Kluge;T. Ungerer
提出了一种嵌入式系统中硬、软、非实时线程并发调度的体系结构。它基于与英飞凌TriCore兼容的超标量有序处理器二进制。该体系结构允许对硬实时线程进行严格的静态WCET分析。无论如何，为了提供高性能，诸如分支预测和乱序执行之类的推测性元素的缺失通过多线程来补偿，将处理器转换为有序SMT处理器。管理调度的优先级控制器能够（1）将固定的时间部分分配给硬实时线程，（2）控制软实时线程的IPC;（3）将执行周期公平地分配给非实时线程。它位于一个单独的单元外的管道，以避免延长的关键path.We评估的处理器使用EEMBC汽车基准测试，并表明，两个软实时线程的重叠可以用来降低时钟速率的23%或授予每个线程65%的单线程IPC。即使主要执行硬实时线程，剩余的资源也可以由并发的软实时线程使用，与单线程执行相比，其性能达到70%。
This paper proposes an architecture for concurrent scheduling of hard, soft and non real-time threads in embedded systems. It is based on a superscalar in-order processor binary compatible to the Infineon TriCore. The architecture allows a tight static WCET analysis of hard real-time threads. To provide high performance anyway, the absence of speculative elements like branch prediction and out-of-order execution is compensated by multithreading, transforming the processor into an in-order SMT processor.The Priority Controller that manages the scheduling is able (1) to assign fixed portions of time to hard real-time threads, (2) to control the IPC of soft real-time threads and (3) to fairly distribute execution cycles to non real-time threads. It is located within a separate unit outside the pipeline to avoid prolonging the critical path.We evaluate the processor using the EEMBC automotive benchmarks and show that the overlapping of two soft real-time threads can be used to either reduce the clock rate by 23% or to grant each thread 65% of its single-threaded IPC. Even if a hard real-time thread is executed predominantly, the remaining resources can be used by concurrent soft real-time threads which reach a performance of 70% compared to their single-threaded execution.