Hardware task scheduling optimizations for reconfigurable computing
Hardware task scheduling optimizations for reconfigurable computing
复制标题
可重构计算的硬件任务调度优化
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
T. El
中科院分区：
文献类型：
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作者：
Miaoqing Huang;H. Simmler;P. Saha;T. El
可重构计算机(RC)可以为域应用程序提供显著的性能改进。然而，由于设计工具的复杂性和所需的硬件设计经验，今天psilas RCS在领域科学家中的广泛接受受到了阻碍。这些系统的硬件/软件协同设计方法的最新发展提供了易用性，但它们在性能上无法与手动协同设计相提并论。本文旨在提高分配给FPGA的硬件任务的整体性能。特别是对任务间通信以及任务之间的数据依赖关系的分析，减少了配置的数量，最大限度地减少了通信开销和任务处理时间。这项工作利用RC和可重构硬件(RH)领域中开发的算法来解决硬件资源的有效使用问题，提出了两种算法，基于权重的调度(WBS)和最高优先级优先-下一步匹配(HPF-NF)。然而，仅靠传统的基于资源的调度不足以降低性能瓶颈，因此需要一种综合的算法。针对依赖分析和任务间通信优化问题，提出了简化数据移动调度(RDMS)算法。仿真结果表明，与WBS和HPF-NF相比，RDMS能够分别减少30%和11%的FPGA配置来调度具有重权节点的随机生成的图。此外，在SGI RC100可重构计算机上实现的13节点复杂任务图的概念验证表明，RDMS不仅能够将必要的配置量从6个减少到4个，而且通信开销减少了48%，硬件处理时间减少了33%。
Reconfigurable computers (RC) can provide significant performance improvement for domain applications. However, wide acceptance of todaypsilas RCs among domain scientist is hindered by the complexity of design tools and the required hardware design experience. Recent developments in hardware/software co-design methodologies for these systems provide the ease of use, but they are not comparable in performance to manual co-design. This paper aims at improving the overall performance of hardware tasks assigned to FPGA. Particularly the analysis of inter-task communication as well as data dependencies among tasks are used to reduce the number of configurations and to minimize the communication overhead and task processing time. This work leverages algorithms developed in the RC and reconfigurable hardware (RH) domains to address efficient use of hardware resources to propose two algorithms, weight-based scheduling (WBS) and highest priority first-next fit (HPF-NF). However, traditional resource based scheduling alone is not sufficient to reduce the performance bottleneck, therefore a comprehensive algorithm is necessary. The reduced data movement scheduling (RDMS) algorithm is proposed to address dependency analysis and inter-task communication optimizations. Simulation shows that compared to WBS and HPF-NF, RDMS is able to reduce the amount of FPGA configurations to schedule random generated graphs with heavy weight nodes by 30% and 11% respectively. Additionally, the proof-of-concept implementation of a complex 13-node example task graph on the SGI RC100 reconfigurable computer shows that RDMS is not only able to trim down the amount of necessary configurations from 6 to 4 but also to reduce communication overhead by 48% and the hardware processing time by 33%.