The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs
The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs
复制标题
外延生长工艺参数对硅钝化Ge pMOSFET 层特性和器件性能的影响
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
R. Loo
中科院分区：
文献类型：
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作者：
M. Caymax;F. Leys;J. Mitard;K. Martens;Lijun Yang;G. Pourtois;W. Vandervorst;M. Meuris;R. Loo
最近，据报道，标准 Si 互补金属氧化物半导体 HfO 2 栅极堆叠模块具有最佳的 65 nm Ge p 沟道金属氧化物半导体场效应晶体管 (pMOSFET) 性能。 Ge 钝化基于在 Ge 表面生长的薄的、完全应变的外延 Si 层。我们更详细地研究了器件性能（空穴迁移率、I on 、D it 、V t 等）如何取决于该 Si 层的特性。我们发现，在生长过程中，Ge 会通过 Si 层发生表面偏析，这决定了最终栅堆叠中的界面陷阱密度和分布。基于对硅沉积工艺基本原理的更好理解，我们通过改用另一种硅前驱体并降低沉积温度来优化工艺。这使得 D it 降低了 4 倍，并提高了器件性能。
Recently, the best 65 nm Ge p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET) performance has been reported with a standard Si complementary metal-oxide-semiconductor HfO 2 gate stack module. The Ge passivation is based on a thin, fully strained epitaxial Si layer grown on the Ge surface. We investigate in more detail how the device performance (hole mobility, I on , D it, V t , etc.) depends on the characteristics of this Si layer. We found that surface segregation of Ge through the Si layer takes place during the growth, which turns out to be determining for the interfacial trap density and distribution in the finalized gate stack. Based on a better understanding of the fundamentals of the Si deposition process, we optimize the process by switching to another Si precursor and lowering the deposition temperature. This results in a 4 times lower D it and improved device performance.