A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory
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DOI：
10.1109/tvlsi.2015.2464092
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发表时间：
2016-04
影响因子：
2.8
通讯作者：
Kin-Chu Ho;Chih-Lung Chen;Hsie-Chia Chang
中科院分区：
文献类型：
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作者：
Kin-Chu Ho;Chih-Lung Chen;Hsie-Chia Chang
拉丁平方算法是一种构造低密度奇偶校验（LDPC）码的算法，具有码长、码率高、纠错能力强、错误层低等优点，但其子矩阵大，在拟合NAND闪存应用时，硬件实现会受到较大的桶移和较差的路由拥塞的影响。本文提出了一种自顶向下的设计方法，该方法不仅通过代码构建和优化，而且通过硬件实现来满足所有关键需求。提出了一种两步阵列色散算法，用于构造子矩阵较小的长LDPC码。然后，利用掩蔽矩阵对所构造的LDPC码进行优化，以获得更好的误码率（BER）性能和更低的误码率。此外，我们的LDPC码在奇偶校验矩阵中具有类似对角线的结构，因此提出了一种混合存储架构，该架构具有更好的区域效率和足够大的数据带宽，可以实现高解码吞吐量。为了应用于NAND闪存，构建了码率为0.9、子矩阵尺寸为63的（18900,17010）LDPC码，并通过现场可编程门阵列仿真，成功地将误码率下限抑制到10-12。在UMC 90纳米CMOS工艺中实现了一种基于归一化最小和可变节点中心顺序调度解码算法的LDPC解码器。后置结果表明，在时钟频率为166.6 MHz的情况下，所提出的LDPC解码器在6次迭代时的吞吐量为1.58 Gb/s，门数为520k。同时满足Toggle双数据速率1.0的NAND闪存和open NAND闪存接口2.3 NAND接口的吞吐量要求。
Although Latin square is a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and low error floor, it has a drawback of large submatrix that the hardware implementation will be suffered from large barrel shifter and worse routing congestion in fitting NAND flash applications. In this paper, a top-down design methodology, which not only goes through code construction and optimization, but also hardware implementation to meet all the critical requirements, is presented. A two-step array dispersion algorithm is proposed to construct long LDPC codes with a small submatrix size. Then, the constructed LDPC code is optimized by masking matrix to obtain better bit-error rate (BER) performance and lower error-floor. In addition, our LDPC codes have a diagonal-like structure in the parity-check matrix leading to a proposed hybrid storage architecture, which has the advantages of better area efficiency and large enough data bandwidth for high decoding throughput. To be adopted for NAND flash applications, an (18900, 17010) LDPC code with a code-rate of 0.9 and submatrix size of 63 is constructed and the field-programmable gate array simulations show that the error floor is successfully suppressed down to BER of 10-12. An LDPC decoder using normalized min-sum variable-node-centric sequential scheduling decoding algorithm is implemented in UMC 90-nm CMOS process. The postlayout result shows that the proposed LDPC decoder can achieve a throughput of 1.58 Gb/s at six iterations with a gate count of 520k under a clock frequency of 166.6 MHz. It meets the throughput requirement of both NAND flash memories with Toggle double data rate 1.0 and open NAND flash interface 2.3 NAND interfaces.