Very-low-voltage testing for weak CMOS logic ICs
Very-low-voltage testing for weak CMOS logic ICs
复制标题
针对弱 CMOS 逻辑 IC 的超低电压测试
DOI：
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发表时间：
1993
期刊：
影响因子：
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通讯作者：
E. McCluskey
中科院分区：
文献类型：
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作者：
Hong Hao;E. McCluskey
在本文中，我们提出了一种CMOS逻辑ic的极低压（VLV）测试技术。研究了CMOS逻辑电路在存在电阻性短路和热载流子损伤情况下的电压依赖性。结果表明，在某些远低于正常的电源电压下，由于这些缺陷的存在，较弱的CMOS逻辑ic可能会被迫故障，而真正好的ic则继续工作。极低电压测试还可以检测由电阻性短路引起的模式相关故障。由于其简单性，并且没有相关的开销，极低压测试可以很容易地应用于芯片和电路板，作为生产测试，现场测试或故障诊断技术
In this paper we propose a very-low-voltage (VLV) testing technique for CMOS logic ICs. Voltage dependence of CMOS logic circuit operation in the presence of resistive shorts and hot carrier damage is studied. It is shown that at certain much-lower-than-normal power supply voltage, weak CMOS logic ICs due to the presence of these flaws can be forced to malfunction while truly good ICs continue to function. Very-low-voltage testing also detects pattern dependent faults caused by resistive shorts. Because of its simplicity and because there is no overhead associated with it, very-low-voltage testing can easily be applied to chips and circuit boards as a production test, field test, or failure diagnosis technique.<<ETX>>