A CAD framework for generating self-checking multipliers based on residue codes
A CAD framework for generating self-checking multipliers based on residue codes
复制标题
基于残差码生成自检乘法器的CAD框架
DOI：
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发表时间：
1999
期刊：
影响因子：
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通讯作者：
M. Nicolaidis
中科院分区：
文献类型：
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作者：
I. Alzaher;M. Nicolaidis
与自检电路设计相关的基本缺点包括高硬件成本和设计工作量。基于奇偶预测兼容方案的自检运算符的最新发展允许我们在对大多数基本数据路径块(例如加法器、ALU、移位器、寄存器堆等)的自检数据路径中实现高故障覆盖率和低硬件成本。然而，奇偶预测自检乘法器涉及的硬件开销比其他块高得多。因此，较大的乘法器将显著增加整个数据路径的硬件开销。剩余算术代码可以降低这一成本，本文提出的工具使用这种代码自动生成自检乘法器。它们使用对各种其他块的奇偶校验预测来完善我们的工具，并支持自动生成低成本的自检数据路径。
The basic drawbacks related to the design of self-checking circuits include high hardware cost and design effort. Recent developments on self-checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware cost in self-checking data paths for the majority of basic data path blocks such as, adders, ALUs, shifters, register files, etc. However, parity prediction self-checking multipliers involve hardware overhead significantly higher than for other blocks. Thus, large multipliers will increase significantly the hardware overhead of the whole data path. Residue arithmetic codes allow to reduce this cost The tools presented in this paper generate automatically self-checking multipliers using such codes. They complete our tools using parity prediction for various other blocks, and enable automatic generation of low cost self-checking data paths.