Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor
复制标题
在 RISC-V 微处理器上使用基于协同设计的故障注入技术进行信息泄漏分析
DOI：
10.1109/tcad.2021.3065915
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发表时间：
2021
影响因子：
2.9
通讯作者：
Brian Dziki
中科院分区：
文献类型：
--
作者：
J. Plusquellic;Donald E. Owen;T. Mannos;Brian Dziki
RISC-V指令集架构开放许可政策催生了开发活动的蜂巢，使RISC-V运营的环境相应地扩展了一系列实施。 RISC-V在不利的操作条件下或正常磨损期后的实现。永久或暂时观察执行行为。启用快速，可配置的故障仿真并利用它进行信息泄漏和数据损坏分析的架构。建立一个评估平台，其中控制元素在处理器上仅使用可编程逻辑中的目标设计（PL）运行。 VI-Indrument的实现是创建和配置的，以执行高级加密标准和Twister算法。输出模拟故障的子集。
The RISC-V instruction set architecture open licensing policy has spawned a hive of development activity, making a range of implementations publicly available. The environments in which RISC-V operates have expanded correspondingly, driving the need for a generalized approach to evaluating the reliability of RISC-V implementations under adverse operating conditions or after normal wear-out periods. Fault injection (FI) refers to the process of changing the state of registers or wires, either permanently or momentarily, and then observing execution behavior. The analysis provides insight into the development of countermeasures that protect against the leakage or corruption of sensitive information, which might occur because of unexpected execution behavior. In this article, we develop a hardware–software co-design architecture that enables fast, configurable fault emulation and utilize it for information leakage and data corruption analysis. Modern system-on-chip FPGAs enable building an evaluation platform, where control elements run on a processor(s) (PS) simultaneously with the target design running in the programmable logic (PL). Software components of the FI system introduce faults and report execution behavior. A pair of RISC-V FI-instrumented implementations are created and configured to execute the Advanced Encryption Standard and Twister algorithms. Key and plaintext information leakage and degraded pseudorandom sequences are both observed in the output for a subset of the emulated faults.