Analyzing cycle stealing on synchronous circuits with level-sensitive latches
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
复制标题
分析具有电平敏感锁存器的同步电路上的周期窃取
DOI：
10.1109/dac.1992.227772
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发表时间：
1992
期刊：
影响因子：
--
通讯作者：
K. Eng
中科院分区：
文献类型：
--
作者：
I. Lin;J. A. Ludwig;K. Eng
提出了一种在电平敏感同步电路设计的时序分析中充分挖掘周期盗用机会的新方法。该算法首先通过对组合逻辑的时序分析来构造锁存图，然后基于锁存节点之间的覆盖时序关系分析周期窃取。广度优先搜索检查锁存中所有可能的周期窃取。该算法还考虑了周期窃取与拓扑相关的事实。时序分析程序还考虑了时钟宽度的变化以及每个锁存器中的前沿和训练时钟沿，因此数据可用于辅助物理设计。该程序已在IBM RISC System/6000与IBM IC设计系统相结合的机上实现。结果表明，在设计中利用周期窃取机会的好处。
The authors present a new method to fully explore cycle steal opportunities in the timing analysis for level-sensitive synchronous circuit designs. The algorithm first constructs a latch graph from a timing analysis on the combinational logic, and then it analyzes cycle stealing based on overlay timing relationships among latch nodes. A breadth-first search examines all possible cycle stealing among latches. The algorithm also considers the fact that cycle stealing is topology dependent. The timing analysis program also takes into account the variation of clock width and leading and training clock edges in each latch, so the data can be used to assist physical design. The program has been implemented on an IBM RISC System/6000 coupled with an IBM IC design system. The results showed the benefit of using cycle steal opportunities in the design.<<ETX>>