Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements
Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements
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用于时间间隔测量的多级脉冲收缩时间数字转换器
DOI：
10.1109/ecwt.2007.4404018
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
Robert Weigel
中科院分区：
文献类型：
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作者：
Yue Liu;U. Vollenbruch;Yangjian Chen;C. Wicpalek;Linus Maurer;Z. Boos;Robert Weigel
提出了一种采用英飞凌0.13微米工艺实现的20ps分辨率脉冲收缩时间数字转换器(TDC)的新结构。这种带反馈环和高速计数器的新型内插多级TDC加速了输入时间间隔的数字化，适合作为锁相环应用的鉴相器。内插式多级结构有效地节省了芯片面积和功耗。其满量程(FSR)约为5000ps，微分线性度误差小于0.52LSB。
This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 mum CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.